Cryo-ASIC Design
ASICs tailored for cryogenic operation
Our ASIC capabilities
Cryo-optimised analogue & digital design
We design both analogue and mixed-signal ASICs using CMOS process nodes, tailored, characterised and validated for operation down to mK temperatures. Our designs achieve ultra-low power dissipation — essential when every milliwatt of heat load matters inside your cooling system.
Standard CMOS — deliberately
We build on commercially available CMOS foundry processes rather than exotic technologies. This gives you supply chain stability, multi-source availability, and a well-understood reliability track record — critical for long-lived quantum computing deployments.
Cryogenic packaging
Die packaging is often an afterthought — not with us. We select and validate packaging materials and interfaces for mechanical and thermal performance at cryogenic temperatures, ensuring robust electrical connections and long operational lifetimes in extreme environments.
Fully customised to your stack
Every quantum hardware architecture is different. We work closely with your team to understand your qubit platform, control topology, and system-level constraints — then design an ASIC that fits precisely into your cryostat.
How we work
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We map your system requirements: qubit count, gate fidelity targets, power budget, operating temperature stage.
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we propose a circuit architecture and walk you through the trade-offs before a single transistor is laid out.
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Full custom ASIC layout, DRC/LVS clean, submitted to foundry.
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We test and validate performance at temperature in our own cryogenic test infrastructure.
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We support you through system integration into your cryostat.